1. Field of the Invention
The present invention relates generally to data converters and in particular to reference current and circuit common compensation in a digital-to-analog data converter.
2. Description of Related Art
D/A converters frequently rely upon a reference voltage applied to some sort of resistive ladder network to provide analog output voltages or currents which are a function of the digital input to the converter. One type of resistive ladder is commonly referred to as a R2R ladder which relies on simple binary weighting. However, this approach is not always suitable for data converters having a relatively high resolution due, by way of example, to the tight matching requirements for the ladder resistances. Prior art segmented architectures as shown in FIG. 1 can be used for high resolution applications, where the resistive ladder network includes an MSB section 8A and an LSB section 8B. The 16 bit binary input to be converted is partitioned into 4 MSBs for network 8A and 12 LSBs for network section 8B.
The 4 MSBs for section 8A are decoded from binary to a 15 bit thermometer code (decoder not depicted) which produces 15 bits. Thus, when the binary code is incremented starting at all zeros, the 15 bit thermometer codes changes one bit at a time as follows: 0 . . . 0000 to 0 . . . 0001 to 0 . . . 0011 to 0 . . . 0111 to 0 . . . 1111 until finally 1 . . . 1111. The 15 bits operate to control the state of switches S1 to S15, either connecting an associated 2R resistive segment terminal to a reference voltage Vref′ bus 16 or to a circuit common Vss bus 18. The resistive segments of section 8A are sometimes referred to herein as segments 1-15, with the R2R LSB section 8B being collectively referred to herein as segment 0.
The 12 LSBs for section 8B are not decoded but are used directly to control the states of respective switches SR0 to SR11. These switches operate to connect the associated 2R resistance to either the reference voltage Vref′ bus 16 or the circuit common Vss bus 18. The two sections 8A and 8B are connected to a common output Vo which is then fed to an output amplifier as will be described.
The FIG. 1 resistive ladder network 8 can be used to operate in either a voltage or a current mode, depending upon the configuration of the output amplifier. FIG. 2 shows a prior art D/A converter 10A using network 8 in the voltage mode configuration. The output Vo of the network is connected to the input of an operational amplifier 12 configured as a unity gain buffer. The buffer presents a high input impedance to the output of the ladder network so that no current is drawn out of the network output Vo, i.e., I2=0. Thus, output voltage Vout of buffer 12 has a magnitude which is equal to the Thevenin equivalent voltage produced by the network for a given digital input.
FIG. 3 shows a prior art D/A converter 10B which includes the FIG. 1 resistive ladder network 8 configured to operate in a current mode. In this case the output Vo of the ladder network 8 is connected to the inverting input of an operational amplifier 14. Feedback provided by resistor Rf forces the amplifier inverting input voltage to be equal to the non-inverting input voltage Vmid, with Vmid typically being Vref′/2 when only a positive supply is being used. Unlike the voltage mode configuration, the current mode configuration produces a current I5 from network 8 which is essentially the analog output of the converter. This output current is converted to a voltage dropped across resistor Rf to produce the output Vout which varies about the mid-voltage Vref′/2.
Both of the voltage and current mode configurations are capable of providing good performance. FIG. 2 shows the voltage mode converter 10A implemented in integrated circuit (IC) form, with the boundaries of the IC being depicted by block 24. As is common, the reference voltage source 22 is disposed outside the IC, typically on the same circuit board on which the IC is mounted. The resistive ladder network 8 draws a current I1 from the source 22. It has been found that this current results in a voltage drop across the electrical connection resistance RB between the source 22 and the IC terminal 20 for receiving Vref. In addition, current I1 further results in a voltage drop across a parasitic resistance RP within the IC between the terminal 20 and the reference voltage bus 16. As shown in FIG. 1, bus 16 distributes the reference voltage throughout both the MSB portion 8A and the LSB 8B portion of the resistive ladder network.
The voltage drops across resistors RB and RP can be sufficiently significant to appreciably reduce the accuracy of the D/A converter 10A. FIG. 4 illustrates one prior art solution to this problem. The integrated circuit 24 is provided with an operational amplifier 24 configured as a non-inverting unity gain buffer. The reference voltage originating from the source 22 external to the IC is again applied to the IC terminal 20 by way of an electrical connection that has a resistance RB. The non-inverting input of amplifier 24 is also connected to the terminal 20, with the inverting input connected to the reference voltage bus 16 of the network so that essentially all of the electrical connection having resistance RP is disposed between the non-inverting input and the output of the amplifier. Since the amplifier input is a high impedance, no current is drawn through resistance RB so that the voltage at terminal 20 is almost exactly voltage Vref. The high amplifier gain in combination with the feedback will force the inverting input voltage to be equal to that of the non-inverting input. Thus, the voltage Vref′ at the reference voltage bus 16 will be maintained at Vref regardless of any current flow through resistance RP.
Although the FIG. 4 solution eliminates errors due to variations in the reference voltage at the ladder input 12, the operational amplifier, which must be of a relatively high performance, can add noise to the system and consumes additional power. In addition, this approach requires that Vref be maintained below the amplifier supply voltage. The various embodiment of the present invention provide an alternative solution to this problem as will become apparent to those skilled in the art upon a reading of the following Detailed Description of the Invention together with the drawings.